Free and Simple Verilog Simulation

icarus verilog logo

In our college labs, we use Xilinx Vivado but for practising Verilog programming at home, at the beginner level that we are, we don’t really need to install Vivado on our systems.
I will be using this tutorial for Ubuntu 18.04, but the same solution works on MacOS and Windows as well (link: https://www.swarthmore.edu/NatSci/mzucker1/e15_f2014/iverilog.html).

REQUIRED SOFTWARE

We will use the following software to code, compile, run, and visualise our verilogfiles:

  • ICARUS VERILOG( iverilog compiler )
    <http://iverilog.icarus.com/>
    It is a Verilog compiler developed by Stephen Williams. It has a feature complete compiler with a test suite available.
  • VS Code
    Visual Studio Code is a free code editor from Microsoft. With a pluginVerilog HDL written for VS Code by Masahiro H, we have:

    • full Verilog syntax highlighting
    • templates
    • code completion.
      In other words, better code editing experience than even Vivado!
  •  GTKWave
    “GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.”(- http://gtkwave.sourceforge.net/)

INSTALLATION

Verilog/iVerilog and GTKWave:

This can be done on Ubuntu in one easy command:
sudo apt install verilog gtkwave

VS CODE

There are two ways to go about this.

Install from the official website
Install using ubuntu-make

This is my preferred method. ubuntu-make is a tool, especially for developers. It keeps their development environments primed and updated automatically.

  • visit: https://github.com/ubuntu/ubuntu-make
  • add the daily build repo for ubuntu-make by running this command in terminal:
    sudo add-apt-repository ppa:lyzardking/ubuntu-make
  • update the repository and install ubuntu make:
    sudo apt update
    sudo apt install ubuntu-make
  • Install VSCode:
    umake ide visual-studio-code
  • Done

Now we will look into installing Verilog HDL plugin and Verilog simulation workflow.

WORKFLOW

I made a video to show how easy this is:

 

I will keep updating this post with working codes for all the labs that we did.

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